DRAM Latency Model¶
In this page, we will explain how we design and implement DRAM latency model (embedded DRAM).
DRAM model provides abstract class, so you can implement your own DRAM latency model by inherit the class.
By default, we provide
SimpleDRAM, similar to
DRAMCtrl of gem5.
AbstractDRAM class is defined in
It defines four virtual functions (+ three virtual functions derived from
You can handle DRAM read/write access request at
isScheduling function defined for ICL, to avoid DRAM conflict when latency calculation.
SimpleDRAM uses two latency parameters of DRAM -
DDR bus bandwidth is calculated by several parameters.
SimpleSSD::DRAM::SimpleDRAM::SimpleDRAM for more details.